This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-087404, filed Mar. 27, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a transistor in which the gate electrode is formed by a damascene gate process, i.e., a burying method, and a method of manufacturing the same.
In recent years, a large scale integrated circuit (LSI) in which a large number of transistors, resistors, etc. are connected to form an electric circuit and are integrated on an single chip is used in an important portion of a computer or a communication equipment. Therefore, the performance of the entire equipment is deeply related to the performance of the LSI body. The performance of the LSI body can be improved by increasing the degree of integration, i.e., by miniaturizing the element. When it comes to, for example, a MOS field effect transistor (MOS transistor), the miniaturization of the element can be achieved by decreasing the gate length and by decreasing the thickness of the source-drain regions.
A low acceleration ion implantation method is widely employed as a method of forming shallow source-drain regions. Source-drain regions having a depth not larger than 0.1 xcexcm can be formed by this method. However, the impurity diffusion layer formed by the low acceleration ion implantation method has a high sheet resistance of at least 100 xcexa9/cm2, making it difficult to achieve a high speed operation by the miniaturization. Such being the situation, a salicide is employed for decreasing the resistance of the source-drain-gate in a device requiring a high speed operation such as a LOGIC-LSI. The term xe2x80x9csalicidexe2x80x9d noted above denotes that a silicide film is formed by self-alignment on the surfaces of the source-drain diffusion layers and the gate electrode (n+ or p+ polycrystalline silicon).
In the case of employing a dual gate, in which an n+ polycrystalline silicon (polysilicon) and a p+ polysilicon are used as the underlying layers of the silicide layer within the same layer, the salicide structure permits not only decreasing the resistance of the gate electrode but also simplifying the process. The particular effect can be obtained because the employment of the salicide structure makes it possible to achieve doping of an impurity into the gate polysilicon in the step of an impurity doping in the source-drain regions. On the other hand, in the case of employing a W polycide as a gate electrode, it is necessary to perform at different timings the step of dividing the polysilicon in the bottom portion of the gate electrode into an n+ doping and a p+ doping and the step of dividing the source-drain into an n+ doping and a p+ doping. It follows that additional steps are required including two times of the lithography step, two times of the ion implantation step, and two times of the resist removing step.
On the other hand, SAC (self-aligned contact) is absolutely required in the device requiring the design of a high density element such as a memory LSI. In the SAC structure, the gate electrode surface must not be exposed to the outside in the step of forming a contact hole in an insulating film on the source or drain region. Therefore, it is necessary to form a silicon nitride layer, which acts as a stopper film in the step of subjecting a silicon oxide film to a reactive ion etching (RIE), on the gate electrode surface. It follows that, in the case of a memory LSI, it is impossible to apply the salicide used in the LOGIC-LSI to the gate electrode.
It was customary in the past to use a polysilicon layer doped with an impurity in the memory LSI. Also, in view of the necessity for decreasing the resistance, employed is a W polycide structure in which a W silicide is laminated on the polysilicon layer. Where the resistance is further decreased, employed is a polymetal structure in which an ultra thin barrier metal layer is formed on the polysilicon layer and a W film is laminated on the barrier metal layer. The polymetal structure has a resistivity lower than that of the structure prepared by laminating a silicide film on the polysilicon layer, making it possible to achieve a desired sheet resistance with a smaller film thickness. However, a dual gate is required in the LOGIC-LSI. Therefore, it is necessary to perform an impurity doping to the polysilicon layer in the gate and to the source-drain regions at different timings, leading to a marked increase in the manufacturing cost.
In an LSI in which a LOGIC and a DRAM are mounted together, if a salicide is attached to the source-drain regions in the DRAM, a pn junction leak current is increased in the memory cell portion, leading to a lowered retaining characteristics. Also, a W polycide is used in the gate electrode because of the particular construction of the SAC structure described above. On the other hand, in the LOGIC, it is necessary to lower the threshold voltage of the MOSFET because current is allowed to flow as much as possible under a low voltage. Such being the situation, the polysilicon of the polycide is doped with P or As in the n-channel MOSFET to use the polysilicon as an n+-silicon layer and is doped with BF3 in the p-channel MOSFET to use the polysilicon as a p+-silicon layer.
Incidentally, DRAM requires a large heat budget after formation of the gate electrode. Therefore, in the case of using the gate electrode structure in which a polysilicon layer forms the lowermost layer, two problems given below are generated in the heating step after formation of the gate electrode.
First of all, impurity atoms such as As atoms and P atoms are outwardly diffused from the polysilicon layer into the W silicide layer, leading to reduction in the impurity concentration in the polysilicon layer. As a result, a depletion layer is expanded within the gate electrode in the step of applying voltage so as to deplete the gate. It follows that the gate capacitance is rendered smaller than the actual value determined by the gate insulating film.
A second problem is that boron atoms within the polysilicon layer are diffused through the gate insulating film so as to reach the silicon substrate. As a result, the distribution in the impurity concentration in the channel region is changed so as to change the threshold voltage of the MOSFET. The inward diffusion of the boron atoms (B) is promoted in the case where F or hydrogen are present together with B. Incidentally, where nitrogen is added to the gate insulating film, a Bxe2x80x94N bond is formed at the interface between the polysilicon layer and the gate insulating film because the Bxe2x80x94N bond is strong, with the result that the inward diffusion of B is suppressed.
The two problems described above can be summarized as follows:
(1) A gate electrode is required independently for each of the LOGIC-LSI and the memory LSI, making it impossible to use a common gate electrode; and
(2) The gate depletion and the inward diffusion of B are generated in the case of employing the polycide or polymetal structure.
Various measures are being proposed for solving the problems given above. For example, proposed is a so-called xe2x80x9cmetal gatexe2x80x9d in which a metal material, not a semiconductor material, is formed directly on the gate insulating film. It is certainly possible to solve the problems derived from the inactivation of the impurities and the impurity diffusion by using the metal gate. However, it is difficult to achieve a precise gate processing in the case of the metal gate.
A method of using a dummy gate is also known to the art. In this method, a dummy gate is formed first, followed by forming source-drain regions and an interlayer insulating film. Then, the surface of the dummy gate is exposed to the outside and the dummy gate is removed, followed by forming a new metal gate film.
Incidentally, the damascene gate process is a process that facilitates the application of the metal gate and an insulating film having a high dielectric constant. However, where the clearance between the contact and the wiring is small and, thus, SAC is required like a high density memory, a problem is generated as follows. Specifically, where, for example, a W/TiN laminate structure is used as a gate electrode, the surface of the W layer is exposed to the outside. In order to avoid the exposure, it is necessary to remove a portion of a surface layer of the W layer, and then, to form a film having an etching rate lower than that of an oxide film. For example, it is necessary to form a silicon nitride film. However, if the thickness of the gate electrode is not larger than 100 nm, it is difficult to control the recess etching amount of the W layer, giving rise to an unevenness of about xc2x130 nm. As a result, the sheet resistance of the gate is rendered markedly uneven such that the sheet resistance falls within a range of between 1 and 10 xcexa9/cm2. In addition, the number of process steps is increased to include the steps of recess etching/wet processing/CVD of silicon nitride film/CMP/wet processing.
The method by the conventional technology will now be described with reference to FIGS. 1A to 1D. It should be noted that, in FIGS. 1A to 1D, the portions of the element isolating insulating film, source-drain regions, a well, a channel, and a gate side wall spacer are omitted from the actual manufacturing process of a transistor.
In the first step, an insulating film 72 having a thickness of 70 to 200 nm is formed on a silicon semiconductor substrate 71, followed by flattening the surface of the insulating film 72, as shown in FIG. 1A. Further, a groove for burying a gate electrode is formed in the insulating film 72, and a gate insulating film 73 consisting of a silicon oxide film, a silicon nitride film or a silicon oxynitride film (SiON) is formed in the bottom portion of the groove. Then, a barrier metal film 74 such as a TiN film and a W film 75 having a low resistivity are formed on the entire surface, followed by removing the undesired metal films other than those inside the groove by CMP or MP.
In the next step, the surface region of the W film 75 is removed in a thickness of about 20 nm to 100 nm by RIE or a wet etching, followed by removing the remaining barrier metal film 74 by a wet etching such that the upper surface of the barrier metal layer 74 is flush with the upper surface of the W layer 75, as shown in FIG. 1B.
Further, a silicon nitride film 76 is deposited on the entire surface in a thickness of 30 nm to 150 nm by an LP-CVD method or a P-CVD method as shown in FIG. 1C, followed by removing the undesired portion of the silicon nitride film 76 by a CMP method or an MP method, as shown in FIG. 1D.
In the case of employing the method described above, additional steps of recess etching is performed two times, an additional CVD step for forming a silicon nitride film is performed, and an additional step of CMP is also performed, leading to an increase in the number of process steps and to an increased RPT (raw process time). It follows that the manufacturing cost of the semiconductor device is increased.
In order to avoid the increase in the manufacturing cost, a method of using an Al electrode is known to the art. However, since Al has a low melting point of 660xc2x0 C., it is necessary to carry out the heat treating step after formation of the Al gate at temperatures not higher than 600xc2x0 C. It follows that, in the case of selecting Al as the metal, the Al gate is incapable of withstanding the heat treating step of 600 to 650xc2x0 C. required in the step of forming a PZT or BST capacitor after the gate formation.
An object of the present invention is to provide a semiconductor device with a high degree of integration, comprising a gate electrode having a high resistance to heat and having a small distance between the gate of a metal gate transistor and the source-drain contact.
Another object of the present invention is to provide a method of manufacturing a semiconductor device with a high degree of integration, comprising a gate electrode having a high resistance to heat and having a small distance between the gate of a metal gate transistor and the source-drain contact, the method making it possible to manufacture the particular semiconductor device by a simplified manufacturing process without increasing RPT.
According to a first aspect of the present invention, there is provided a semiconductor device, comprising:
a semiconductor substrate;
an insulating film formed on the semiconductor substrate and a gate electrode formed on the insulating film;
source-drain regions formed in the semiconductor substrate; and
a metal oxide layer formed selectively on the gate electrode;
wherein the gate electrode is formed of a first metal, and the metal oxide layer contains a second metal having a reduction amount in a Gibbs standard free energy in forming an oxide larger than that of the first metal.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode containing a first metal on a semiconductor substrate with an insulating film interposed therebetween;
forming source-drain regions in the semiconductor substrate; and
selectively forming a metal oxide layer containing a second metal on the gate electrode;
wherein the second metal has a reduction amount in a Gibbs standard free energy in forming an oxide larger than that of the first metal.
In the present invention, it is desirable for the first metal to be at least one metal selected from the group consisting of W, Mo, Ru, Ag, and Cu.
Also, it is desirable for the second metal to be at least one metal selected from the group consisting of Al, Ti, Zr, Hf, Nb, Ta, Ba, Sr, Y and La series elements. The La series elements include La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu.
In the semiconductor device of the present invention, it is desirable for the thickness of the metal oxide layer to be 1 to 50 nm.
Further, it is desirable for the semiconductor device of the present invention to comprise an interlayer insulating film consisting of a silicon oxide film, and it is also desirable for the second metal to have a reduction amount in a Gibbs standard free energy in forming an oxide larger than that of the material forming the interlayer insulating film.
It is possible for the semiconductor device of the present invention to comprise a layer of a third metal or a compound of the third metal formed in the bottom surface of the gate electrode. In this case, it is desirable for the third metal not to be alloyed or not to form a compound with the first metal. Also, the crystal grain diameter of the third metal should desirably be smaller than that of the first metal.
It is also possible for the semiconductor device of the present invention to comprise a layer of a third metal or a compound of the third metal formed on the bottom surface and the side surface of the gate electrode. In this case, it is desirable for the third metal not to be alloyed or not to form a compound with the first metal. Also, the crystal grain diameter of the third metal should desirably be smaller than that of the first metal.
In the method of the present invention for manufacturing a semiconductor device, it is desirable for the metal oxide layer containing the second metal to be formed by the step of implanting ions of the second metal into the gate electrode so as to form an ion implantation layer and the step of selectively oxidizing the ion implantation layer.
Alternatively, it is desirable for the metal oxide layer containing the second metal to be formed by the step of forming a metal film containing the second metal on the gate electrode containing the first metal, the step of forming an alloy film containing the first metal and the second metal on the gate electrode, and the step of selectively oxidizing the alloy film.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.